THE NAND GATE

The NAND gate is another logic device commonly found in digital equipment. This gate is simply an AND gate with an inverter (NOT gate) at the output.

LOGIC SYMBOL

The logic symbol for the NAND gate is shown in figure 2-11.

Figure 2-11. - NAND gate.

The NAND gate can have two or more inputs. The output will be LOW only when all the inputs are HIGH. Conversely, the output will be HIGH when any or all of the inputs are LOW.

The NAND gate performs two functions, AND and NOT. Separating the NAND symbol to show these two functions would reveal the equivalent circuits depicted in figure 2-12. This should help you better understand how the NAND gate functions.

Figure 2-12. - NAND gate equivalent circuit: A. Either X or Y or both are LOW; B. Both X and Y are HIGH.

Inputs X and Y are applied to the AND gate. If either X or Y or both are LOW (view A), then the output of the AND gate is LOW. A LOW (logic 0) on the input of the inverter results in a HIGH (logic 1) output. When both X and Y are HIGH (view B), the output of the AND gate is HIGH; thus the output of the inverter is LOW. The Boolean expression for the output of a NAND gate with these inputs is f = XY. The expression is spoken "X AND Y quantity NOT." The output of any NAND gate is the negation of the input. For example, if our inputs are X and Y, the output will be

NAND GATE OPERATION

Now, let's observe the logic level inputs and corresponding outputs as shown in figure 2-13. At time T₀, X and Y are both LOW. The output is HIGH; the opposite of an AND gate with the same inputs. At T₁, X goes HIGH and Y remains LOW. As a result, the output remains HIGH. At T₂, X goes LOW and Y goes HIGH. Again, the output remains HIGH. When both X and Y are HIGH at T₄, the output goes LOW. The output will remain LOW only as long as both X and Y are HIGH.

Figure 2-13. - NAND gate input and output signals.

TRUTH TABLE

The Truth Table for a NAND gate with X and Y as inputs is shown below.

F = XY

Q.16 A NAND gate has Z and X as inputs. What will be the output logic level if Z is HIGH and X is LOW?
Q.17 What must be the state of the inputs to a NAND gate in order to produce a LOW output?
Q.18 What is the output Boolean expression for a NAND gate with inputs A, B, and C?
Q.19 A NAND gate has inputs labeled as A, B, and C. If A and B are HIGH, C must be at what logic level to produce a HIGH output?