ANSWERS TO QUESTIONS Q1. THROUGH Q64.

A1. .
A2. Low (0).
A3. One or the other of the inputs must be HIGH, but not both at the same time.
A4. Exclusive NOR (X-NOR).
A5. HIGH.
A6. The half adder generates a carry.
A7. Quarter adder.
A8. Sum equals 0 with a carry of 1.
A9. Full adder.
A10. Four.
A11. S₁ = 1, S₂ = 0 and C₂ = 1.
A12. C₁ = 0.
A13. X-OR gates.
A14. Four.
A15. MSD of the sum.
A16. Add 1 portion.
A17. Subtrahend.
A18. Storing information.
A19. Six.
A20. 1 and 0, or opposite states.
A21. By cross-coupling NAND or OR gates.
A22. One.
A23. To divide the input by 2.
A24. Clock and data.
A25. Up to one clock pulse.
A26. A positive-going clock pulse.
A27. J-K flip-flop.

A28. Set, or HIGH (1).
A29. When the clock pulse goes LOW.
A30. Both J and K must be HIGH.
A31. Clear (CLR) and preset (PS or PR).
A32. The flip-flop is jammed.
A33. A timing signal.
A34. An astable or free-running multivibrator.
A35. Triggers.
A36. A multiphase clock.
A37. 32.
A38. Ripple.
A39. Toggle.
A40. Synchronous.
A41. The AND gate.
A42. 1111₂, or 15₁₀.
A43. Four.
A44. FFs 2 and 4.
A45. Two.
A46. Three.
A47. The input, or clock pulse.
A48. One.
A49. Four.
A50. Q output of FF 1 going LOW.
A51. 16.
A52. Parallel.
A53. By clearing the register.
A54. Shift register.
A55. Serial.
A56. Requires more circuitry.
A57. Eight.
A58. Four.
A59. 2², or four times.
A60. Three to the left.
A61. Logic families.
A62. DTL (diode transistor logic).
A63. DIPs (dual inline packages).
A64. Compatible.