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FLIP-FLOPS Flip-flops (FFs) are devices used in the digital field for a variety of purposes. When properly connected, flip-flops may be used to store data temporarily, to multiply or divide, to count operations, or to receive and transfer information. Flip-flops are bistable multivibrators. The types used in digital equipment are identified by the inputs. They may have from two up to five inputs depending on the type. They are all common in one respect. They have two, and only two, distinct output states. The outputs are normally labeled Q and Q and should always be complementary. When Q = 1, then Q = 0 and vice versa. In this section we will discuss four types of FFs that are common to digital equipment. They are the R-S, D, T, and J-K FFs. R-S FLIP-FLOP The R-S FF is used to temporarily hold or store information until it is needed. A single R-S FF will store one binary digit, either a 1 or a 0. Storing a four-digit binary number would require four R-S FFs. The standard symbol for the R-S FF is shown in figure 3-12, view A. The name is derived from the inputs, R for reset and S for set. It is often referred to as an R-S LATCH. The outputs Q and Q are complements, as mentioned earlier. Figure 3-12. - R-S flip-flop: A. Standard symbol; B. R-S FF with inverted inputs.
The R-S FF has two output conditions. When the Q output is HIGH and Q is LOW, the FF is set. When Q is LOW and Q is HIGH, the FF is reset. When the R and S inputs are both LOW, the Q and Q outputs will both be HIGH. When this condition exists, the FF is considered to be JAMMED and the outputs cannot be used. The jammed condition is corrected when either S or R goes HIGH. To set the flip-flop requires a HIGH on the S input and a LOW on the R input. To reset, the opposite is required; S input LOW and R input HIGH. When both R and S are HIGH, the FF will hold or "latch" the condition that existed before both inputs went HIGH. Because the S input of this FF requires a logic LOW to set, a more easily understood symbol is shown in figure 3-12, view B. Refer to this view while reading the following paragraph. In our description of R-S FF operation, let's assume that the signals applied to the S and R inputs are the LSDs of two different binary numbers. Let's also assume that these two binary numbers represent the speed and range of a target ship. The LSDs will be called SB0 (Speed Bit 0) and RB0 (Range Bit 0) and will be applied to the S and R inputs respectively. Refer to figure 3-12, view B, and figure 3-13. At time T0, both SB0 and RB0 are HIGH, as a result, both Q and Q are HIGH. This is the jammed state and as mentioned earlier, cannot be used in logic circuitry. At T1, SB0 goes LOW and RB0 remains HIGH; Q goes LOW and Q remains HIGH; the FF is reset. At T2 RB0 goes LOW and SB0 remains LOW; the FF is latched in the reset condition. At T3, SB0 goes HIGH and RB0 remains LOW; the FF sets. At T4 SB0 goes LOW and RB0 goes HIGH; the FF resets. When SB0 and RB0 input conditions reverse at T5, the FF sets. The circuit is put in the latch condition at T6 when SB0 goes LOW. Notice that the output changes states ONLY when the inputs are in opposite states. Figure 3-13. - R-S flip-flop with inverted inputs timing diagram.
Figure 3-14 shows two methods of constructing an R-S FF. We can use these diagrams to prove the Truth Table for the R-S FF. Figure 3-14. - R-S FF construction: A. Using cross-coupled NAND gates; B. Using cross-coupled OR gates.
Look at figure 3-14, view A. Let's assume SB0 is HIGH and RB0 is LOW. You should remember from chapter 2 that the output of an inverter is the complement of the input. In this case, since SB0 is HIGH, SBO will be LOW. The LOW input to NAND gate 1 causes the Q output to go HIGH. This HIGH Q output is also fed to the input of NAND gate 2. The other input to NAND gate 2, RBO , is HIGH. With both inputs to gate 2 HIGH, the output goes LOW. The LOW Q output is also fed to NAND gate 1 to be used as the "latch" signal. If SB0 goes LOW while this condition exists, there will be no change to the outputs because the FF would be in the latched condition; both SB0 and RB0 LOW. When RB0 is HIGH and SB0 is LOW, RBO being LOW drives the output, Q, to a HIGH condition. The HIGH Q and HIGH SBO inputs to gate 1 cause the output, Q, to go LOW. This LOW is also fed to NAND gate 2 to be used as the latch signal. Since SB0 is LOW, the FF will again go into the latched mode if RB0 goes LOW. The cross-coupled OR gates in figure 3-14, view B, perform the same functions as the NAND gate configuration of view A. A HIGH input at SB0 produces a HIGH Q output, and a LOW at RB0 produces a LOW Q output. The cross-coupled signals (Q to gate 1 and Q to gate 2) are used as the latch signals just as in view A. You can trace other changes of the inputs using your knowledge of basic logic gates. Q.18 What are R-S FFs used for? |
 
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