ADDERS

Adders are combinations of logic gates that combine binary values to obtain a sum. They are classified according to their ability to accept and combine the digits. In this section we will discuss quarter adders, half adders, and full adders.

QUARTER ADDER

A quarter adder is a circuit that can add two binary digits but will not produce a carry. This circuit will produce the following results:

0 plus 0 = 0
0 plus 1 = 1
1 plus 0 = 1
1 plus 1 = 0 (no carry)

You will notice that the output produced is the same as the output for the Truth Table of an X-OR. Therefore, an X-OR gate can be used as a quarter adder.

The combination of gates in figure 3-6 will also produce the desired results. When A and B are both LOW (0), the output of each AND gate is LOW (0); therefore, the output of the OR gate is LOW (0). When A is HIGH and B is LOW, then B is HIGH and AND gate 1 produces a HIGH output, resulting in a sum of 1 at gate 3. With A LOW and B HIGH, gate 2 output is HIGH, and the sum is 1. When both A and B are HIGH, neither AND gate has an output, and the output of gate 3 is LOW (0); no carry is produced.

Figure 3-6. - Quarter adder.

HALF ADDER

A half adder is designed to combine two binary digits and produce a carry.

Figure 3-7 shows two ways of constructing a half adder. An AND gate is added in parallel to the quarter adder to generate the carry. The SUM column of the Truth Table represents the output of the quarter adder, and the CARRY column represents the output of the AND gate.

Figure 3-7. - Half adders and Truth Table.

We have seen that the output of the quarter adder is HIGH when either input, but not both, is HIGH. It is only when both inputs are HIGH that the AND gate is activated and a carry is produced. The largest sum that can be obtained from a half adder is 10₂ (1₂ plus 1₂).

FULL ADDER

The full adder becomes necessary when a carry input must be added to the two binary digits to obtain the correct sum. A half adder has no input for carries from previous circuits.

One method of constructing a full adder is to use two half adders and an OR gate as shown in figure 3-8. The inputs A and B are applied to gates 1 and 2. These make up one half adder. The sum output of this half adder and the carry-from a previous circuit become the inputs to the second half adder. The carry from each half adder is applied to gate 5 to produce the carry-out for the circuit.

Figure 3-8. - Full adder and Truth Table.

Now let's add a series of numbers and see how the circuit operates.

First, let's add 1 and 0. When either A or B is HIGH, gate 1 has an output. This output is applied to gates 3 and 4. Since the carry-in is 0, only gate 3 will produce an output. The sum of 1₂ and 0 is 1₂.

Now let's add 1₂ and 1₂. If A and B are both HIGH, the output of gate 1 is LOW. When the carry-in is 0 (LOW), the output of gate 3 is LOW. Gate 2 produces an output that is applied to gate 5, which produces the carry-out. The sum of 1_{2 a}nd 1₂ is 10₂, just as it was for the half adder. When A and B are both LOW and the carry-in is 1, only gate 3 has an output and produces a sum of 1₂ with no carry-out.

Now, let's add A or B and a carry-in. For example, let's assume that A is HIGH and B is LOW. With these conditions, gate 1 will have an output. This output and the carry-in applied to gates 3 and 4 will produce a sum out of 0 and a carry of 1. This carry from gate 4 will cause gate 5 to produce a carry-out. The sum of A and a carry (1₂ plus 1₂) is 10₂.

When A, B, and the carry-in are all HIGH, a sum of 1 and a carry-out are produced. First, consider A and B. When both are HIGH, the output of gate 1 is LOW, and the output of gate 2 is HIGH, giving us a carry-out at gate 5. The carry-in produces a 1 output at gate 3, giving us a sum of 1. The output of the full adder is 11₂. The sum of 1₂ plus 1₂ plus 1₂ is 11₂.

PARALLEL ADDERS

The adders discussed in the previous section have been limited to adding single-digit binary numbers and carries. The largest sum that can be obtained using a full adder is 11₂.

Parallel adders let us add multiple-digit numbers. If we place full adders in parallel, we can add two- or four-digit numbers or any other size desired. Figure 3-9 uses STANDARD SYMBOLS to show a parallel adder capable of adding two, two-digit binary numbers. In previous discussions we have depicted circuits with individual logic gates shown. Standard symbols (blocks) allow us to analyze circuits with inputs and outputs only. One standard symbol may actually contain many and various types of gates and circuits. The addend would be input on the A inputs (A₂ = MSD, A₁ = LSD), and the augend input on the B inputs (B₂ = MSD, B ₁ = LSD). For this explanation we will assume there is no input to C₀ (carry from a previous circuit).

Figure 3-9. - Parallel binary adder.

Now let's add some two-digit numbers. To add 10₂ (addend) and 01₂ (augend), assume there are numbers at the appropriate inputs. The addend inputs will be 1 on A₂ and 0 on A₁. The augend inputs will be 0 on B₂ and 1 on B₁. Working from right to left, as we do in normal addition, let's calculate the outputs of each full adder.

With A₁ at 0 and B₁ at 1, the output of adder 1 will be a sum (S₁) of 1 with no carry (C₁). Since A₂ is 1 and B₂ is 0, we have a sum (S₂) of 1 with no carry (C₂) from adder 1. To determine the sum, read the outputs (C₂, S ₂, and S₁) from left to right. In this case, C₂ = 0, S₂ = 1, and S₁ = 1. The sum, then, of 10₂ and 01₂ is 011₂ or 11₂.

To add 11₂ and 01₂, assume one number is applied to A₁ and A₂, and the other to B₁ and B₂, as shown in figure 3-10. Adder 1 produces a sum (S₁) of 0 and a carry (C₁) of 1. Adder 2 gives us a sum (S₂) of 0 and a carry (C₂) of 1. By reading the outputs (C₂, S₂, and S₁), we see that the sum of 11₂ and 01₂ is 100₂.

Figure 3-10. - Parallel addition.

As you know, the highest binary number with two digits is 11₂. Using the parallel adder, let's add 11 ₂ and 11₂.

First, apply the addend and augend to the A and B inputs. Calculate the output of each full adder beginning with full adder 1. With A₁ and B₁ at 1, S₁ is 0 and C₁ is 1. Since all three inputs (A₂, B₂, and C₁) to full adder 2 are 1, the output will be 1 at S₂ and 1 at C₂. The output of the circuit, as you read left to right, is 110₂, the sum of 11₂ and 11₂.

Parallel adders may be expanded by combining more full adders to accommodate the number of digits in the numbers to be added. There must be one full adder for each digit.

Q.6 What advantage does a half adder have over a quarter adder?
Q.7 An X-OR gate may be used as what type of adder?
Q.8 What will be the output of a half adder when both inputs are 1s?
Q.9 What type of adder is used to handle a carry from a previous circuit?
Q.10 How many full adders are required to add four-digit numbers?
Q.11 With the inputs shown below, what will be the output of S₁, S₂, and C₂?